February 22 @ 11 a.m. – noon
Dr. Yogendra Joshi
G.W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology
Held in ETRL 101
Refreshments served in ETRL 119 at 10:30 a.m.
Thermal Management and Design Approaches to Enable Heterogeneous 3D Integration
Abstract
With the recent end of the International Technology Roadmap for Semiconductors, which has guided research on thermal packaging of microprocessors for nearly a quarter century, significantly different challenges are on the horizon. Heterogeneous integration promises to bring in multiple functionalities in highly compact form factors via interposer based (2.5D) and three-dimensional (3D) stacked chip approaches. Compared to planar integrated circuits (ICs), 3D stacked ICs as an emerging technology have significant advantages, including shorter interconnection length, smaller power consumption, and higher computation speed. However, chip stacking poses great challenges to thermal management. Increased chip temperatures can degrade the reliability and performance, and increase the leakage power that constitutes a significant part of the total chip power. To mitigate these undesirable effects, advanced thermal management, such as microfluidic cooling can be employed. Very few experimental demonstrations of CMOS chips with integrated microfluidic cooling currently exist. In this presentation, inter-tier microfluidic cooling will be explored as a promising approach for future 3D stacked ICs due to its superior thermal performance and scalability. I will discuss ongoing research on microfluidic single phase and two phase cooling to address the high heat fluxes, and localized hot spots in these applications. Examples of thermal/electrical co-design, which is essential for successful use of this technology will be presented for high performance and mobile applications. For the latter, thermal management and energy conservation must be simultaneously considered. To fully utilize microfluidic cooling, reliable fluid delivery systems and good heat transfer fluids are required. It is concluded that extensive research on integration of inter-tier microfluidic cooling of 3D stacked ICs is still needed.
Biography
With the recent end of the International Technology Roadmap for Semiconductors, which has guided research on thermal packaging of microprocessors for nearly a quarter century, significantly different challenges are on the horizon. Heterogeneous integration promises to bring in multiple functionalities in highly compact form factors via interposer based (2.5D) and three-dimensional (3D) stacked chip approaches. Compared to planar integrated circuits (ICs), 3D stacked ICs as an emerging technology have significant advantages, including shorter interconnection length, smaller power consumption, and higher computation speed. However, chip stacking poses great challenges to thermal management. Increased chip temperatures can degrade the reliability and performance, and increase the leakage power that constitutes a significant part of the total chip power. To mitigate these undesirable effects, advanced thermal management, such as microfluidic cooling can be employed. Very few experimental demonstrations of CMOS chips with integrated microfluidic cooling currently exist. In this presentation, inter-tier microfluidic cooling will be explored as a promising approach for future 3D stacked ICs due to its superior thermal performance and scalability. I will discuss ongoing research on microfluidic single phase and two phase cooling to address the high heat fluxes, and localized hot spots in these applications. Examples of thermal/electrical co-design, which is essential for successful use of this technology will be presented for high performance and mobile applications. For the latter, thermal management and energy conservation must be simultaneously considered. To fully utilize microfluidic cooling, reliable fluid delivery systems and good heat transfer fluids are required. It is concluded that extensive research on integration of inter-tier microfluidic cooling of 3D stacked ICs is still needed.
