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$800,000 NSF grant

Researchers aim to speed computing, lower energy use

Thursday, May 17, 2012

By Dan Estep, College of Engineering and Architecture intern
 
PULLMAN, Wash. - A group of Washington State University researchers have received an $800,000 National Science Foundation grant for work to improve the speed and lower the power use of computer processors.
 
Pande
Led by Associate Professor Partha Pande from the School of Electrical Engineering and Computer Science and collaborators from the Georgia institute of technology and the Rochester Institute of Technology, the team also includes associate professors Deukhyoun Heo and Benjamin Belzer.
 
Worldwide implications
The implications of the technology will be felt around the world, says Pande. The majority of the processors designed today are multicore, which means they are made up of several processing cores. One of their major performance limitations stems from the multihop nature of intercore data exchange. That is, data has to move around several cores, slowing down the processor and wasting energy.
 
The researchers hope their work in on-chip wireless communication networks will significantly improve the speed of such processors while also reducing power consumption.
 
Identifying multicore limitations
Since receiving his Ph.D. from the University of British Columbia in 2005, Pande has focused his research on network-on-chip, which is the enabling technology for integrating many embedded cores on a single chip.
 
He realized there were limitations with multicore processors with growing levels of integration, including high power consumption and delays in processing. In 2007, he began looking into a new solution that will shift the paradigm with on-chip wireless links.
 
Connecting nodes directly
Multicore processors traditionally use multihop wired connections between nodes. The proposed architecture will use wireless shortcuts to communicate between the distant nodes instead. This means single-hop links effectively bypass the intermediary nodes and will directly connect one node to another.
 
Heo Belzer
"The big question is how to design the single-hop shortcuts,” Pande said. To solve this question he and his two collaborators, WSU associate professors Deukhyoun Heo and Benjamin Belzer are working to introduce the so-called Small World Architecture.
 
"Small World Architecture uses communication highways to improve multicore processor performance,” Pande said. "You have regular, wired links, but you also need to establish long range shortcuts. The wireless links are those shortcuts.”
 
Along with designing the wireless shortcuts, Pande and his team also need to design a low-power transceiver, on-chip antennas and communication protocols for the wireless shortcuts to work. Once these are in place, this concept can be applied on a much larger scale.
 
 

Contact:
Partha Pande, associate professor, WSU School of Electrical Engineering and Computer Science, 509-335-5223, partha_pande@wsu.edu
Tina Hilding, public relations coordinator, WSU College of Engineering and Architecture, 509-335-5095, thilding@wsu.edu

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